From 272d56301097fafd4ec64cdd032a426686a429ca Mon Sep 17 00:00:00 2001 From: Clint Chance Date: Sun, 12 Jul 2026 17:15:03 -0500 Subject: [PATCH] Fix TXSerialFlush1/2 so they actually wait for transmission to complete. Both functions passed a flag constant (USART_FLAG_TXE) to USART_GetITStatus() and span while TXE was set - but TXE being set means the data register is already empty, so the loop exited immediately with data still queued in the software FIFO and shifting out of the USART. flush therefore never waited at all. Wait for the software TX FIFO to drain and then for the TC flag, which indicates the shift register has actually emptied. --- SerialSTM.cpp | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/SerialSTM.cpp b/SerialSTM.cpp index 61c20d3..9bd4af2 100644 --- a/SerialSTM.cpp +++ b/SerialSTM.cpp @@ -103,8 +103,12 @@ uint16_t RXSerialfifolevel1() // warning: this call is blocking void TXSerialFlush1() { - // wait until the TXE shows the shift register is empty - while (USART_GetITStatus(USART1, USART_FLAG_TXE)) + // wait until the TX FIFO has drained + while (TXSerialfifolevel1() > 0U) + ; + + // wait until the TC flag shows the shift register is empty + while (USART_GetFlagStatus(USART1, USART_FLAG_TC) == RESET) ; } @@ -294,8 +298,12 @@ uint16_t RXSerialfifolevel2() // warning: this call is blocking void TXSerialFlush2() { - // wait until the TXE shows the shift register is empty - while (USART_GetITStatus(USART2, USART_FLAG_TXE)) + // wait until the TX FIFO has drained + while (TXSerialfifolevel2() > 0U) + ; + + // wait until the TC flag shows the shift register is empty + while (USART_GetFlagStatus(USART2, USART_FLAG_TC) == RESET) ; }