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402 lines
14 KiB
402 lines
14 KiB
/*
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* Copyright (C) 2018 Jonathan Brandenburg
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/* Warning: This file is automatically generated by AX-RadioLAB.
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Manual changes are overwritten! */
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#include "config.h"
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#include "../axradio/axradioinit.h"
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#include "../spi/ax5043spi.h"
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#include "../crc/crc.h"
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// TX: fcarrier=435.300MHz dev= 13.600kHz br= 4.800kBit/s pwr= 15.0dBm
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// RX: fcarrier=435.300MHz bw= 28.200kHz br= 4.800kBit/s
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void ax5043_set_registers(void)
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{
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ax5043WriteReg(AX5043_MODULATION, 0x08);
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ax5043WriteReg(AX5043_ENCODING, 0x00);
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ax5043WriteReg(AX5043_FRAMING, 0x24);
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ax5043WriteReg(AX5043_FEC, 0x13);
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ax5043WriteReg(AX5043_PINFUNCSYSCLK, 0x01);
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ax5043WriteReg(AX5043_PINFUNCDCLK, 0x01);
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ax5043WriteReg(AX5043_PINFUNCDATA, 0x01);
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ax5043WriteReg(AX5043_PINFUNCANTSEL, 0x01);
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ax5043WriteReg(AX5043_PINFUNCPWRAMP, 0x01);
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ax5043WriteReg(AX5043_WAKEUPXOEARLY, 0x01);
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ax5043WriteReg(AX5043_IFFREQ1, 0x06);
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ax5043WriteReg(AX5043_IFFREQ0, 0x04);
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ax5043WriteReg(AX5043_DECIMATION, 0x07);
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ax5043WriteReg(AX5043_RXDATARATE2, 0x00);
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ax5043WriteReg(AX5043_RXDATARATE1, 0xEE);
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ax5043WriteReg(AX5043_RXDATARATE0, 0x18);
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ax5043WriteReg(AX5043_MAXDROFFSET2, 0x00);
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ax5043WriteReg(AX5043_MAXDROFFSET1, 0x00);
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ax5043WriteReg(AX5043_MAXDROFFSET0, 0x00);
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ax5043WriteReg(AX5043_MAXRFOFFSET2, 0x80);
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ax5043WriteReg(AX5043_MAXRFOFFSET1, 0x23);
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ax5043WriteReg(AX5043_MAXRFOFFSET0, 0xA9);
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ax5043WriteReg(AX5043_FSKDMAX1, 0x05);
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ax5043WriteReg(AX5043_FSKDMAX0, 0x76);
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ax5043WriteReg(AX5043_FSKDMIN1, 0xFA);
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ax5043WriteReg(AX5043_FSKDMIN0, 0x8A);
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ax5043WriteReg(AX5043_AMPLFILTER, 0x00);
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ax5043WriteReg(AX5043_RXPARAMSETS, 0xF4);
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ax5043WriteReg(AX5043_AGCGAIN0, 0xC6);
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ax5043WriteReg(AX5043_AGCTARGET0, 0x84);
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ax5043WriteReg(AX5043_TIMEGAIN0, 0xEA);
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ax5043WriteReg(AX5043_DRGAIN0, 0xE4);
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ax5043WriteReg(AX5043_PHASEGAIN0, 0xC3);
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ax5043WriteReg(AX5043_FREQUENCYGAINA0, 0x0F);
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ax5043WriteReg(AX5043_FREQUENCYGAINB0, 0x1F);
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ax5043WriteReg(AX5043_FREQUENCYGAINC0, 0x0A);
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ax5043WriteReg(AX5043_FREQUENCYGAIND0, 0x0A);
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ax5043WriteReg(AX5043_AMPLITUDEGAIN0, 0x06);
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ax5043WriteReg(AX5043_FREQDEV10, 0x00);
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ax5043WriteReg(AX5043_FREQDEV00, 0x00);
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ax5043WriteReg(AX5043_BBOFFSRES0, 0x00);
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ax5043WriteReg(AX5043_AGCGAIN1, 0xC6);
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ax5043WriteReg(AX5043_AGCTARGET1, 0x84);
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ax5043WriteReg(AX5043_AGCAHYST1, 0x00);
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ax5043WriteReg(AX5043_AGCMINMAX1, 0x00);
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ax5043WriteReg(AX5043_TIMEGAIN1, 0xE8);
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ax5043WriteReg(AX5043_DRGAIN1, 0xE3);
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ax5043WriteReg(AX5043_PHASEGAIN1, 0xC3);
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ax5043WriteReg(AX5043_FREQUENCYGAINA1, 0x0F);
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ax5043WriteReg(AX5043_FREQUENCYGAINB1, 0x1F);
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ax5043WriteReg(AX5043_FREQUENCYGAINC1, 0x0A);
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ax5043WriteReg(AX5043_FREQUENCYGAIND1, 0x0A);
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ax5043WriteReg(AX5043_AMPLITUDEGAIN1, 0x06);
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ax5043WriteReg(AX5043_FREQDEV11, 0x02);
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ax5043WriteReg(AX5043_FREQDEV01, 0x36);
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ax5043WriteReg(AX5043_FOURFSK1, 0x16);
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ax5043WriteReg(AX5043_BBOFFSRES1, 0x00);
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ax5043WriteReg(AX5043_AGCGAIN3, 0xFF);
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ax5043WriteReg(AX5043_AGCTARGET3, 0x84);
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ax5043WriteReg(AX5043_AGCAHYST3, 0x00);
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ax5043WriteReg(AX5043_AGCMINMAX3, 0x00);
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ax5043WriteReg(AX5043_TIMEGAIN3, 0xE7);
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ax5043WriteReg(AX5043_DRGAIN3, 0xE2);
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ax5043WriteReg(AX5043_PHASEGAIN3, 0xC3);
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ax5043WriteReg(AX5043_FREQUENCYGAINA3, 0x0F);
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ax5043WriteReg(AX5043_FREQUENCYGAINB3, 0x1F);
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ax5043WriteReg(AX5043_FREQUENCYGAINC3, 0x0D);
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ax5043WriteReg(AX5043_FREQUENCYGAIND3, 0x0D);
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ax5043WriteReg(AX5043_AMPLITUDEGAIN3, 0x06);
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ax5043WriteReg(AX5043_FREQDEV13, 0x02);
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ax5043WriteReg(AX5043_FREQDEV03, 0x36);
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ax5043WriteReg(AX5043_FOURFSK3, 0x16);
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ax5043WriteReg(AX5043_BBOFFSRES3, 0x00);
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ax5043WriteReg(AX5043_MODCFGF, 0x03);
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ax5043WriteReg(AX5043_FSKDEV2, 0x00);
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ax5043WriteReg(AX5043_FSKDEV1, 0x37);
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ax5043WriteReg(AX5043_FSKDEV0, 0xB5);
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ax5043WriteReg(AX5043_MODCFGA, 0x05);
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ax5043WriteReg(AX5043_TXRATE2, 0x00);
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ax5043WriteReg(AX5043_TXRATE1, 0x13);
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ax5043WriteReg(AX5043_TXRATE0, 0xA9);
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ax5043WriteReg(AX5043_TXPWRCOEFFB1, 0x0F);
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ax5043WriteReg(AX5043_TXPWRCOEFFB0, 0xFF);
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ax5043WriteReg(AX5043_PLLVCOI, 0x99);
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ax5043WriteReg(AX5043_PLLRNGCLK, 0x03);
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ax5043WriteReg(AX5043_BBTUNE, 0x0F);
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ax5043WriteReg(AX5043_BBOFFSCAP, 0x77);
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ax5043WriteReg(AX5043_PKTADDRCFG, 0x00);
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ax5043WriteReg(AX5043_PKTLENCFG, 0x80);
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ax5043WriteReg(AX5043_PKTLENOFFSET, 0x00);
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ax5043WriteReg(AX5043_PKTMAXLEN, 0xC8);
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ax5043WriteReg(AX5043_MATCH0PAT3, 0xAA);
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ax5043WriteReg(AX5043_MATCH0PAT2, 0xCC);
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ax5043WriteReg(AX5043_MATCH0PAT1, 0xAA);
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ax5043WriteReg(AX5043_MATCH0PAT0, 0xCC);
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ax5043WriteReg(AX5043_MATCH1PAT1, 0x7E);
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ax5043WriteReg(AX5043_MATCH1PAT0, 0x7E);
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ax5043WriteReg(AX5043_MATCH1LEN, 0x8A);
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ax5043WriteReg(AX5043_MATCH1MAX, 0x0A);
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ax5043WriteReg(AX5043_TMGTXBOOST, 0x32);
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ax5043WriteReg(AX5043_TMGTXSETTLE, 0x14);
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ax5043WriteReg(AX5043_TMGRXBOOST, 0x32);
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ax5043WriteReg(AX5043_TMGRXSETTLE, 0x14);
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ax5043WriteReg(AX5043_TMGRXOFFSACQ, 0x00);
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ax5043WriteReg(AX5043_TMGRXCOARSEAGC, 0x73);
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ax5043WriteReg(AX5043_TMGRXRSSI, 0x03);
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ax5043WriteReg(AX5043_TMGRXPREAMBLE2, 0x17);
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ax5043WriteReg(AX5043_RSSIABSTHR, 0xE6);
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ax5043WriteReg(AX5043_BGNDRSSITHR, 0x00);
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ax5043WriteReg(AX5043_PKTCHUNKSIZE, 0x0D);
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ax5043WriteReg(AX5043_PKTACCEPTFLAGS, 0x20);
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ax5043WriteReg(AX5043_DACVALUE1, 0x00);
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ax5043WriteReg(AX5043_DACVALUE0, 0x00);
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ax5043WriteReg(AX5043_DACCONFIG, 0x00);
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ax5043WriteReg(AX5043_REF, 0x03);
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ax5043WriteReg(AX5043_XTALOSC, 0x03);
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ax5043WriteReg(AX5043_XTALAMPL, 0x07);
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ax5043WriteReg(AX5043_0xF1C, 0x07);
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ax5043WriteReg(AX5043_0xF21, 0x68);
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ax5043WriteReg(AX5043_0xF22, 0xFF);
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ax5043WriteReg(AX5043_0xF23, 0x84);
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ax5043WriteReg(AX5043_0xF26, 0x98);
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ax5043WriteReg(AX5043_0xF34, 0x28);
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ax5043WriteReg(AX5043_0xF35, 0x10);
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ax5043WriteReg(AX5043_0xF44, 0x25);
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}
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void ax5043_set_registers_tx(void)
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{
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ax5043WriteReg(AX5043_PLLLOOP, 0x09);
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ax5043WriteReg(AX5043_PLLCPI, 0x02);
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ax5043WriteReg(AX5043_PLLVCODIV, 0x24);
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ax5043WriteReg(AX5043_XTALCAP, 0x0C);
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ax5043WriteReg(AX5043_0xF00, 0x0F);
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ax5043WriteReg(AX5043_0xF18, 0x06);
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}
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void ax5043_set_registers_rx(void)
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{
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ax5043WriteReg(AX5043_PLLLOOP, 0x0B);
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ax5043WriteReg(AX5043_PLLCPI, 0x10);
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ax5043WriteReg(AX5043_PLLVCODIV, 0x24);
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ax5043WriteReg(AX5043_XTALCAP, 0x0C);
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ax5043WriteReg(AX5043_0xF00, 0x0F);
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ax5043WriteReg(AX5043_0xF18, 0x02);
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}
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void ax5043_set_registers_rxwor(void)
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{
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ax5043WriteReg(AX5043_TMGRXAGC, 0x37);
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ax5043WriteReg(AX5043_TMGRXPREAMBLE1, 0x19);
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ax5043WriteReg(AX5043_PKTMISCFLAGS, 0x03);
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}
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void ax5043_set_registers_rxcont(void)
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{
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ax5043WriteReg(AX5043_TMGRXAGC, 0x00);
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ax5043WriteReg(AX5043_TMGRXPREAMBLE1, 0x00);
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ax5043WriteReg(AX5043_PKTMISCFLAGS, 0x00);
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}
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void ax5043_set_registers_rxcont_singleparamset(void)
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{
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ax5043WriteReg(AX5043_RXPARAMSETS, 0xFF);
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ax5043WriteReg(AX5043_FREQDEV13, 0x00);
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ax5043WriteReg(AX5043_FREQDEV03, 0x00);
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ax5043WriteReg(AX5043_AGCGAIN3, 0xE8);
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}
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#define MUL8_16(x,y) ((uint8_t)((x)&0xff)*(uint16_t)(uint8_t)((y)&0xff))
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#define CONSTMULFIX24(x) \
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if (f >= 0) { \
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uint32_t r = MUL8_16((x)>>16,f); \
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r += MUL8_16((x)>>8,f>>8); \
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r += MUL8_16((x),f>>16); \
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r >>= 8; \
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r += MUL8_16((x)>>24,f); \
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r += MUL8_16((x)>>16,f>>8); \
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r += MUL8_16((x)>>8,f>>16); \
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r += MUL8_16((x),f>>24); \
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r += ((uint32_t)MUL8_16((x)>>24,f>>8))<<8; \
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r += ((uint32_t)MUL8_16((x)>>16,f>>16))<<8; \
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r += ((uint32_t)MUL8_16((x)>>8,f>>24))<<8; \
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r += ((uint32_t)MUL8_16((x)>>24,f>>16))<<16; \
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r += ((uint32_t)MUL8_16((x)>>16,f>>24))<<16; \
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r += ((uint32_t)MUL8_16((x)>>24,f>>24))<<24; \
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return r; \
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} \
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{ \
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int32_t r; \
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f = -f; \
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r = -(uint32_t)MUL8_16((x)>>16,f); \
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r -= (uint32_t)MUL8_16((x)>>8,f>>8); \
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r -= (uint32_t)MUL8_16((x),f>>16); \
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r >>= 8; \
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r -= (uint32_t)MUL8_16((x)>>24,f); \
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r -= (uint32_t)MUL8_16((x)>>16,f>>8); \
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r -= (uint32_t)MUL8_16((x)>>8,f>>16); \
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r -= (uint32_t)MUL8_16((x),f>>24); \
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r -= ((uint32_t)MUL8_16((x)>>24,f>>8))<<8; \
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r -= ((uint32_t)MUL8_16((x)>>16,f>>16))<<8; \
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r -= ((uint32_t)MUL8_16((x)>>8,f>>24))<<8; \
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r -= ((uint32_t)MUL8_16((x)>>24,f>>16))<<16; \
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r -= ((uint32_t)MUL8_16((x)>>16,f>>24))<<16; \
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r -= ((uint32_t)MUL8_16((x)>>24,f>>24))<<24; \
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return r; \
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}
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#define CONSTMULFIX16(x) \
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if (f >= 0) { \
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uint32_t r = MUL8_16((x)>>16,f); \
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r += MUL8_16((x)>>8,f>>8); \
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r >>= 8; \
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r += MUL8_16((x)>>24,f); \
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r += MUL8_16((x)>>16,f>>8); \
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r += ((uint32_t)MUL8_16((x)>>24,f>>8))<<8; \
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return r; \
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} \
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{ \
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int32_t r; \
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f = -f; \
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r = -(uint32_t)MUL8_16((x)>>16,f); \
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r -= (uint32_t)MUL8_16((x)>>8,f>>8); \
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r >>= 8; \
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r -= (uint32_t)MUL8_16((x)>>24,f); \
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r -= (uint32_t)MUL8_16((x)>>16,f>>8); \
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r -= ((uint32_t)MUL8_16((x)>>24,f>>8))<<8; \
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return r; \
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}
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int32_t axradio_conv_freq_fromhz(int32_t f)
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{
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/* scale by 1.048576 (true 1.048576) */
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CONSTMULFIX24(0x10c6f7a);
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}
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int32_t axradio_conv_freq_tohz(int32_t f)
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{
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/* scale by 0.953674 (true 0.953674) */
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CONSTMULFIX24(0xf42400);
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}
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const uint8_t axradio_phy_innerfreqloop = 0;
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int32_t axradio_conv_freq_fromreg(int32_t f)
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{
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/* scale by 1.000000 (true 1.000000) */
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CONSTMULFIX16(0x1000000);
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}
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int32_t axradio_conv_timeinterval_totimer0(int32_t dt)
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{
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/* scale by 0.032776 (true 0.032768) */
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int32_t r;
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dt >>= 5;
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r = dt;
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dt >>= 4;
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r += dt;
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dt >>= 2;
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r -= dt;
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dt >>= 3;
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r += dt;
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return r;
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}
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uint8_t axradio_byteconv(uint8_t b)
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{
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return b;
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}
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void axradio_byteconv_buffer(uint8_t *buf __attribute__((unused)), uint16_t buflen __attribute__((unused)))
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{
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}
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uint16_t axradio_framing_check_crc(uint8_t *pkt, uint16_t cnt)
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{
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if (crc_crc16(pkt, cnt, 0xFFFF) != 0xB001)
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return 0;
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return cnt;
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}
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uint16_t axradio_framing_append_crc(uint8_t *pkt, uint16_t cnt)
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{
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uint16_t s = 0xFFFF;
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s = crc_crc16(pkt, cnt, s);
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pkt += cnt;
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*pkt++ = ~(uint8_t)(s);
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*pkt++ = ~(uint8_t)(s >> 8);
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return cnt + 2;
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}
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// physical layer
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const uint8_t axradio_phy_pn9 = 0;
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const uint8_t axradio_phy_nrchannels = 1;
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const uint32_t axradio_phy_chanfreq[1] = { 0x1b34cccd };
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const uint8_t axradio_phy_chanpllrnginit[1] = { 0x0a };
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const uint8_t axradio_phy_chanvcoiinit[1] = { 0x99 };
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uint8_t axradio_phy_chanpllrng[1];
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uint8_t axradio_phy_chanvcoi[1];
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const uint8_t axradio_phy_vcocalib = 0;
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const int32_t axradio_phy_maxfreqoffset = 27387;
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const int8_t axradio_phy_rssioffset = 64;
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// axradio_phy_rssioffset is added to AX5043_RSSIREFERENCE and subtracted from chip RSSI value to prevent overflows (8bit RSSI only goes down to -128)
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// axradio_phy_rssioffset is also added to AX5043_RSSIABSTHR
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const int8_t axradio_phy_rssireference = (int8_t)(0xF8 + 64);
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const int8_t axradio_phy_channelbusy = -90 + 64;
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const uint16_t axradio_phy_cs_period = 7; // timer0 units, 10ms
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const uint8_t axradio_phy_cs_enabled = 0;
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const uint8_t axradio_phy_lbt_retries = 0;
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const uint8_t axradio_phy_lbt_forcetx = 0;
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const uint16_t axradio_phy_preamble_wor_longlen = 2; // wor_longlen + wor_len totals to 240.0ms plus 112bits
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const uint16_t axradio_phy_preamble_wor_len = 176;
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const uint16_t axradio_phy_preamble_longlen = 0;
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const uint16_t axradio_phy_preamble_len = 112;
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const uint8_t axradio_phy_preamble_byte = 0x7e;
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const uint8_t axradio_phy_preamble_flags = 0x38;
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const uint8_t axradio_phy_preamble_appendbits = 0;
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const uint8_t axradio_phy_preamble_appendpattern = 0x00;
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//framing
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const uint8_t axradio_framing_maclen = 1;
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const uint8_t axradio_framing_addrlen = 0;
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const uint8_t axradio_framing_destaddrpos = 0;
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const uint8_t axradio_framing_sourceaddrpos = 0xff;
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const uint8_t axradio_framing_lenpos = 0;
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const uint8_t axradio_framing_lenoffs = 0;
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const uint8_t axradio_framing_lenmask = 0xff;
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const uint8_t axradio_framing_swcrclen = 0;
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const uint8_t axradio_framing_synclen = 32;
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const uint8_t axradio_framing_syncword[] = { 0xcc, 0xaa, 0xcc, 0xaa};
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const uint8_t axradio_framing_syncflags = 0x18;
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const uint8_t axradio_framing_enable_sfdcallback = 0;
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const uint32_t axradio_framing_ack_timeout = 65; // 98.9ms in wtimer0 units (640Hz)
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const uint32_t axradio_framing_ack_delay = 313; // 1.0ms in wtimer1 units (20MHz/64)
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const uint8_t axradio_framing_ack_retransmissions = 0;
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const uint8_t axradio_framing_ack_seqnrpos = 0xff;
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const uint8_t axradio_framing_minpayloadlen = 0; // must be set to 1 if the payload directly follows the destination address, and a CRC is configured
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//WOR
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const uint16_t axradio_wor_period = 128;
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// synchronous mode
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const uint32_t axradio_sync_period = 32768; // ACTUALLY FREQ, NOT PERIOD!
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const uint32_t axradio_sync_xoscstartup = 49;
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const uint32_t axradio_sync_slave_syncwindow = 98304; // 3.000s
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const uint32_t axradio_sync_slave_initialsyncwindow = 5898240; //180.000s
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const uint32_t axradio_sync_slave_syncpause = 19660800; // 600.000s
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const int16_t axradio_sync_slave_maxperiod = 2020; // in (2^SYNC_K1) * wtimer0 units
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const uint8_t axradio_sync_slave_resyncloss = 11; // resyncloss is one more than the number of missed packets to cause a resync
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// window 0 is the first window after synchronisation
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// window 1 is the window normally used when there are no lost packets
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// window 2 is used after one packet is lost, etc
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const uint8_t axradio_sync_slave_nrrx = 3;
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const uint32_t axradio_sync_slave_rxadvance[] = { 1833, 1796, 1874 };// 55.918ms, 54.788ms, 57.167ms
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const uint32_t axradio_sync_slave_rxwindow[] = { 1847, 1773, 1929 }; // 56.346ms, 54.086ms, 58.844ms
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const uint32_t axradio_sync_slave_rxtimeout = 3032; // 92.5ms, maximum duration of a packet
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