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429 lines
24 KiB
429 lines
24 KiB
// Copyright (c) 2018 Brandenburg Tech, LLC
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// All rights reserved.
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//
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// THIS SOFTWARE IS PROVIDED BY BRANDENBURG TECH, LLC AND CONTRIBUTORS
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// ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL BRANDENBURT TECH, LLC
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// AND CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Copyright (c) 2007,2008,2009,2010,2011,2012,2013, 2014 AXSEM AG
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1.Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// 2.Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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// 3.Neither the name of AXSEM AG, Duebendorf nor the
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// names of its contributors may be used to endorse or promote products
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// derived from this software without specific prior written permission.
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// 4.All advertising materials mentioning features or use of this software
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// must display the following acknowledgement:
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// This product includes software developed by AXSEM AG and its contributors.
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// 5.The usage of this source code is only granted for operation with AX5043
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// and AX8052F143. Porting to other radio or communication devices is
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// strictly prohibited.
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//
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// THIS SOFTWARE IS PROVIDED BY AXSEM AG AND CONTRIBUTORS ``AS IS'' AND ANY
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// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL AXSEM AG AND CONTRIBUTORS BE LIABLE FOR ANY
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// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#ifndef AX5043INIT_H_
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#define AX5043INIT_H_
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#include <stdint.h>
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#define AXRADIO_MODE_UNINIT 0x00
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#define AXRADIO_MODE_OFF 0x01
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#define AXRADIO_MODE_DEEPSLEEP 0x02
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#define AXRADIO_MODE_CW_TRANSMIT 0x03
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#define AXRADIO_MODE_ASYNC_TRANSMIT 0x10
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#define AXRADIO_MODE_WOR_TRANSMIT 0x11
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#define AXRADIO_MODE_ACK_TRANSMIT 0x12
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#define AXRADIO_MODE_WOR_ACK_TRANSMIT 0x13
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#define AXRADIO_MODE_STREAM_TRANSMIT_UNENC 0x18
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#define AXRADIO_MODE_STREAM_TRANSMIT_SCRAM 0x19
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#define AXRADIO_MODE_STREAM_TRANSMIT_UNENC_LSB 0x1A
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#define AXRADIO_MODE_STREAM_TRANSMIT_SCRAM_LSB 0x1B
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#define AXRADIO_MODE_STREAM_TRANSMIT 0x1C
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#define AXRADIO_MODE_ASYNC_RECEIVE 0x20
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#define AXRADIO_MODE_WOR_RECEIVE 0x21
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#define AXRADIO_MODE_ACK_RECEIVE 0x22
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#define AXRADIO_MODE_WOR_ACK_RECEIVE 0x23
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#define AXRADIO_MODE_STREAM_RECEIVE_UNENC 0x28
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#define AXRADIO_MODE_STREAM_RECEIVE_SCRAM 0x29
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#define AXRADIO_MODE_STREAM_RECEIVE_UNENC_LSB 0x2A
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#define AXRADIO_MODE_STREAM_RECEIVE_SCRAM_LSB 0x2B
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#define AXRADIO_MODE_STREAM_RECEIVE 0x2C
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#define AXRADIO_MODE_STREAM_RECEIVE_DATAPIN 0x2D
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#define AXRADIO_MODE_SYNC_MASTER 0x30
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#define AXRADIO_MODE_SYNC_ACK_MASTER 0x31
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#define AXRADIO_MODE_SYNC_SLAVE 0x32
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#define AXRADIO_MODE_SYNC_ACK_SLAVE 0x33
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#define AX5043_AFSKCTRL 0x114 /* AFSK Control */
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#define AX5043_AFSKMARK0 0x113 /* AFSK Mark (1) Frequency 0 */
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#define AX5043_AFSKMARK1 0x112 /* AFSK Mark (1) Frequency 1 */
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#define AX5043_AFSKSPACE0 0x111 /* AFSK Space (0) Frequency 0 */
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#define AX5043_AFSKSPACE1 0x110 /* AFSK Space (0) Frequency 1 */
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#define AX5043_AGCCOUNTER 0x043 /* AGC Counter */
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#define AX5043_AMPLFILTER 0x115 /* Amplitude Filter */
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#define AX5043_BBOFFSCAP 0x189 /* Baseband Offset Compensation Capacitors */
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#define AX5043_BBTUNE 0x188 /* Baseband Tuning */
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#define AX5043_BGNDRSSI 0x041 /* Background RSSI */
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#define AX5043_BGNDRSSIGAIN 0x22E /* Background RSSI Averaging Time Constant */
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#define AX5043_BGNDRSSITHR 0x22F /* Background RSSI Relative Threshold */
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#define AX5043_CRCINIT0 0x017 /* CRC Initial Value 0 */
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#define AX5043_CRCINIT1 0x016 /* CRC Initial Value 1 */
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#define AX5043_CRCINIT2 0x015 /* CRC Initial Value 2 */
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#define AX5043_CRCINIT3 0x014 /* CRC Initial Value 3 */
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#define AX5043_DACCONFIG 0x332 /* DAC Configuration */
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#define AX5043_DACVALUE0 0x331 /* DAC Value 0 */
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#define AX5043_DACVALUE1 0x330 /* DAC Value 1 */
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#define AX5043_DECIMATION 0x102 /* Decimation Factor */
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#define AX5043_DIVERSITY 0x042 /* Antenna Diversity Configuration */
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#define AX5043_ENCODING 0x011 /* Encoding */
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#define AX5043_FEC 0x018 /* Forward Error Correction */
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#define AX5043_FECSTATUS 0x01A /* Forward Error Correction Status */
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#define AX5043_FECSYNC 0x019 /* Forward Error Correction Sync Threshold */
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#define AX5043_FIFOCOUNT0 0x02B /* Number of Words currently in FIFO 0 */
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#define AX5043_FIFOCOUNT1 0x02A /* Number of Words currently in FIFO 1 */
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#define AX5043_FIFODATA 0x029 /* FIFO Data */
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#define AX5043_FIFOFREE0 0x02D /* Number of Words that can be written to FIFO 0 */
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#define AX5043_FIFOFREE1 0x02C /* Number of Words that can be written to FIFO 1 */
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#define AX5043_FIFOSTAT 0x028 /* FIFO Control */
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#define AX5043_FIFOTHRESH0 0x02F /* FIFO Threshold 0 */
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#define AX5043_FIFOTHRESH1 0x02E /* FIFO Threshold 1 */
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#define AX5043_FRAMING 0x012 /* Framing Mode */
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#define AX5043_FREQA0 0x037 /* Frequency A 0 */
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#define AX5043_FREQA1 0x036 /* Frequency A 1 */
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#define AX5043_FREQA2 0x035 /* Frequency A 2 */
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#define AX5043_FREQA3 0x034 /* Frequency A 3 */
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#define AX5043_FREQB0 0x03F /* Frequency B 0 */
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#define AX5043_FREQB1 0x03E /* Frequency B 1 */
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#define AX5043_FREQB2 0x03D /* Frequency B 2 */
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#define AX5043_FREQB3 0x03C /* Frequency B 3 */
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#define AX5043_FSKDEV0 0x163 /* FSK Deviation 0 */
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#define AX5043_FSKDEV1 0x162 /* FSK Deviation 1 */
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#define AX5043_FSKDEV2 0x161 /* FSK Deviation 2 */
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#define AX5043_FSKDMAX0 0x10D /* Four FSK Rx Maximum Deviation 0 */
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#define AX5043_FSKDMAX1 0x10C /* Four FSK Rx Maximum Deviation 1 */
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#define AX5043_FSKDMIN0 0x10F /* Four FSK Rx Minimum Deviation 0 */
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#define AX5043_FSKDMIN1 0x10E /* Four FSK Rx Minimum Deviation 1 */
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#define AX5043_GPADC13VALUE0 0x309 /* GPADC13 Value 0 */
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#define AX5043_GPADC13VALUE1 0x308 /* GPADC13 Value 1 */
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#define AX5043_GPADCCTRL 0x300 /* General Purpose ADC Control */
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#define AX5043_GPADCPERIOD 0x301 /* GPADC Sampling Period */
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#define AX5043_IFFREQ0 0x101 /* 2nd LO / IF Frequency 0 */
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#define AX5043_IFFREQ1 0x100 /* 2nd LO / IF Frequency 1 */
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#define AX5043_IRQINVERSION0 0x00B /* IRQ Inversion 0 */
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#define AX5043_IRQINVERSION1 0x00A /* IRQ Inversion 1 */
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#define AX5043_IRQMASK0 0x007 /* IRQ Mask 0 */
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#define AX5043_IRQMASK1 0x006 /* IRQ Mask 1 */
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#define AX5043_IRQREQUEST0 0x00D /* IRQ Request 0 */
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#define AX5043_IRQREQUEST1 0x00C /* IRQ Request 1 */
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#define AX5043_LPOSCCONFIG 0x310 /* Low Power Oscillator Calibration Configuration */
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#define AX5043_LPOSCFREQ0 0x317 /* Low Power Oscillator Frequency Tuning Low Byte */
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#define AX5043_LPOSCFREQ1 0x316 /* Low Power Oscillator Frequency Tuning High Byte */
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#define AX5043_LPOSCKFILT0 0x313 /* Low Power Oscillator Calibration Filter Constant Low Byte */
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#define AX5043_LPOSCKFILT1 0x312 /* Low Power Oscillator Calibration Filter Constant High Byte */
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#define AX5043_LPOSCPER0 0x319 /* Low Power Oscillator Period Low Byte */
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#define AX5043_LPOSCPER1 0x318 /* Low Power Oscillator Period High Byte */
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#define AX5043_LPOSCREF0 0x315 /* Low Power Oscillator Reference Frequency Low Byte */
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#define AX5043_LPOSCREF1 0x314 /* Low Power Oscillator Reference Frequency High Byte */
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#define AX5043_LPOSCSTATUS 0x311 /* Low Power Oscillator Calibration Status */
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#define AX5043_MATCH0LEN 0x214 /* Pattern Match Unit 0, Pattern Length */
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#define AX5043_MATCH0MAX 0x216 /* Pattern Match Unit 0, Maximum Match */
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#define AX5043_MATCH0MIN 0x215 /* Pattern Match Unit 0, Minimum Match */
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#define AX5043_MATCH0PAT0 0x213 /* Pattern Match Unit 0, Pattern 0 */
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#define AX5043_MATCH0PAT1 0x212 /* Pattern Match Unit 0, Pattern 1 */
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#define AX5043_MATCH0PAT2 0x211 /* Pattern Match Unit 0, Pattern 2 */
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#define AX5043_MATCH0PAT3 0x210 /* Pattern Match Unit 0, Pattern 3 */
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#define AX5043_MATCH1LEN 0x21C /* Pattern Match Unit 1, Pattern Length */
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#define AX5043_MATCH1MAX 0x21E /* Pattern Match Unit 1, Maximum Match */
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#define AX5043_MATCH1MIN 0x21D /* Pattern Match Unit 1, Minimum Match */
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#define AX5043_MATCH1PAT0 0x219 /* Pattern Match Unit 1, Pattern 0 */
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#define AX5043_MATCH1PAT1 0x218 /* Pattern Match Unit 1, Pattern 1 */
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#define AX5043_MAXDROFFSET0 0x108 /* Maximum Receiver Datarate Offset 0 */
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#define AX5043_MAXDROFFSET1 0x107 /* Maximum Receiver Datarate Offset 1 */
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#define AX5043_MAXDROFFSET2 0x106 /* Maximum Receiver Datarate Offset 2 */
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#define AX5043_MAXRFOFFSET0 0x10B /* Maximum Receiver RF Offset 0 */
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#define AX5043_MAXRFOFFSET1 0x10A /* Maximum Receiver RF Offset 1 */
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#define AX5043_MAXRFOFFSET2 0x109 /* Maximum Receiver RF Offset 2 */
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#define AX5043_MODCFGA 0x164 /* Modulator Configuration A */
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#define AX5043_MODCFGF 0x160 /* Modulator Configuration F */
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#define AX5043_MODCFGP 0xF5F /* Modulator Configuration P */
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#define AX5043_MODULATION 0x010 /* Modulation */
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#define AX5043_PINFUNCANTSEL 0x025 /* Pin Function ANTSEL */
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#define AX5043_PINFUNCDATA 0x023 /* Pin Function DATA */
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#define AX5043_PINFUNCDCLK 0x022 /* Pin Function DCLK */
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#define AX5043_PINFUNCIRQ 0x024 /* Pin Function IRQ */
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#define AX5043_PINFUNCPWRAMP 0x026 /* Pin Function PWRAMP */
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#define AX5043_PINFUNCSYSCLK 0x021 /* Pin Function SYSCLK */
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#define AX5043_PINSTATE 0x020 /* Pin State */
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#define AX5043_PKTACCEPTFLAGS 0x233 /* Packet Controller Accept Flags */
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#define AX5043_PKTCHUNKSIZE 0x230 /* Packet Chunk Size */
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#define AX5043_PKTMISCFLAGS 0x231 /* Packet Controller Miscellaneous Flags */
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#define AX5043_PKTSTOREFLAGS 0x232 /* Packet Controller Store Flags */
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#define AX5043_PLLCPI 0x031 /* PLL Charge Pump Current */
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#define AX5043_PLLCPIBOOST 0x039 /* PLL Charge Pump Current (Boosted) */
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#define AX5043_PLLLOCKDET 0x182 /* PLL Lock Detect Delay */
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#define AX5043_PLLLOOP 0x030 /* PLL Loop Filter Settings */
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#define AX5043_PLLLOOPBOOST 0x038 /* PLL Loop Filter Settings (Boosted) */
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#define AX5043_PLLRANGINGA 0x033 /* PLL Autoranging A */
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#define AX5043_PLLRANGINGB 0x03B /* PLL Autoranging B */
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#define AX5043_PLLRNGCLK 0x183 /* PLL Autoranging Clock */
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#define AX5043_PLLVCODIV 0x032 /* PLL Divider Settings */
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#define AX5043_PLLVCOI 0x180 /* PLL VCO Current */
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#define AX5043_PLLVCOIR 0x181 /* PLL VCO Current Readback */
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#define AX5043_POWCTRL1 0xF08 /* Power Control 1 */
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#define AX5043_POWIRQMASK 0x005 /* Power Management Interrupt Mask */
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#define AX5043_POWSTAT 0x003 /* Power Management Status */
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#define AX5043_POWSTICKYSTAT 0x004 /* Power Management Sticky Status */
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#define AX5043_PWRAMP 0x027 /* PWRAMP Control */
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#define AX5043_PWRMODE 0x002 /* Power Mode */
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#define AX5043_RADIOEVENTMASK0 0x009 /* Radio Event Mask 0 */
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#define AX5043_RADIOEVENTMASK1 0x008 /* Radio Event Mask 1 */
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#define AX5043_RADIOEVENTREQ0 0x00F /* Radio Event Request 0 */
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#define AX5043_RADIOEVENTREQ1 0x00E /* Radio Event Request 1 */
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#define AX5043_RADIOSTATE 0x01C /* Radio Controller State */
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#define AX5043_REF 0xF0D /* Reference */
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#define AX5043_RSSI 0x040 /* Received Signal Strength Indicator */
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#define AX5043_RSSIABSTHR 0x22D /* RSSI Absolute Threshold */
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#define AX5043_RSSIREFERENCE 0x22C /* RSSI Offset */
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#define AX5043_RXDATARATE0 0x105 /* Receiver Datarate 0 */
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#define AX5043_RXDATARATE1 0x104 /* Receiver Datarate 1 */
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#define AX5043_RXDATARATE2 0x103 /* Receiver Datarate 2 */
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#define AX5043_SCRATCH 0x001 /* Scratch */
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#define AX5043_SILICONREVISION 0x000 /* Silicon Revision */
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#define AX5043_TIMER0 0x05B /* 1MHz Timer 0 */
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#define AX5043_TIMER1 0x05A /* 1MHz Timer 1 */
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#define AX5043_TIMER2 0x059 /* 1MHz Timer 2 */
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#define AX5043_TMGRXAGC 0x227 /* Receiver AGC Settling Time */
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#define AX5043_TMGRXBOOST 0x223 /* Receive PLL Boost Time */
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#define AX5043_TMGRXCOARSEAGC 0x226 /* Receive Coarse AGC Time */
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#define AX5043_TMGRXOFFSACQ 0x225 /* Receive Baseband DC Offset Acquisition Time */
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#define AX5043_TMGRXPREAMBLE1 0x229 /* Receiver Preamble 1 Timeout */
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#define AX5043_TMGRXPREAMBLE2 0x22A /* Receiver Preamble 2 Timeout */
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#define AX5043_TMGRXPREAMBLE3 0x22B /* Receiver Preamble 3 Timeout */
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#define AX5043_TMGRXRSSI 0x228 /* Receiver RSSI Settling Time */
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#define AX5043_TMGRXSETTLE 0x224 /* Receive PLL (post Boost) Settling Time */
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#define AX5043_TMGTXBOOST 0x220 /* Transmit PLL Boost Time */
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#define AX5043_TMGTXSETTLE 0x221 /* Transmit PLL (post Boost) Settling Time */
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#define AX5043_TRKAFSKDEMOD0 0x055 /* AFSK Demodulator Tracking 0 */
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#define AX5043_TRKAFSKDEMOD1 0x054 /* AFSK Demodulator Tracking 1 */
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#define AX5043_TRKAMPLITUDE0 0x049 /* Amplitude Tracking 0 */
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#define AX5043_TRKAMPLITUDE1 0x048 /* Amplitude Tracking 1 */
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#define AX5043_TRKDATARATE0 0x047 /* Datarate Tracking 0 */
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#define AX5043_TRKDATARATE1 0x046 /* Datarate Tracking 1 */
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#define AX5043_TRKDATARATE2 0x045 /* Datarate Tracking 2 */
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#define AX5043_TRKFREQ0 0x051 /* Frequency Tracking 0 */
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#define AX5043_TRKFREQ1 0x050 /* Frequency Tracking 1 */
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#define AX5043_TRKFSKDEMOD0 0x053 /* FSK Demodulator Tracking 0 */
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#define AX5043_TRKFSKDEMOD1 0x052 /* FSK Demodulator Tracking 1 */
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#define AX5043_TRKPHASE0 0x04B /* Phase Tracking 0 */
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#define AX5043_TRKPHASE1 0x04A /* Phase Tracking 1 */
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#define AX5043_TRKRFFREQ0 0x04F /* RF Frequency Tracking 0 */
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#define AX5043_TRKRFFREQ1 0x04E /* RF Frequency Tracking 1 */
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#define AX5043_TRKRFFREQ2 0x04D /* RF Frequency Tracking 2 */
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#define AX5043_TXPWRCOEFFA0 0x169 /* Transmitter Predistortion Coefficient A 0 */
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#define AX5043_TXPWRCOEFFA1 0x168 /* Transmitter Predistortion Coefficient A 1 */
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#define AX5043_TXPWRCOEFFB0 0x16B /* Transmitter Predistortion Coefficient B 0 */
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#define AX5043_TXPWRCOEFFB1 0x16A /* Transmitter Predistortion Coefficient B 1 */
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#define AX5043_TXPWRCOEFFC0 0x16D /* Transmitter Predistortion Coefficient C 0 */
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#define AX5043_TXPWRCOEFFC1 0x16C /* Transmitter Predistortion Coefficient C 1 */
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#define AX5043_TXPWRCOEFFD0 0x16F /* Transmitter Predistortion Coefficient D 0 */
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#define AX5043_TXPWRCOEFFD1 0x16E /* Transmitter Predistortion Coefficient D 1 */
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#define AX5043_TXPWRCOEFFE0 0x171 /* Transmitter Predistortion Coefficient E 0 */
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#define AX5043_TXPWRCOEFFE1 0x170 /* Transmitter Predistortion Coefficient E 1 */
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#define AX5043_TXRATE0 0x167 /* Transmitter Bitrate 0 */
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#define AX5043_TXRATE1 0x166 /* Transmitter Bitrate 1 */
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#define AX5043_TXRATE2 0x165 /* Transmitter Bitrate 2 */
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#define AX5043_WAKEUP0 0x06B /* Wakeup Time 0 */
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#define AX5043_WAKEUP1 0x06A /* Wakeup Time 1 */
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#define AX5043_WAKEUPFREQ0 0x06D /* Wakeup Frequency 0 */
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#define AX5043_WAKEUPFREQ1 0x06C /* Wakeup Frequency 1 */
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#define AX5043_WAKEUPTIMER0 0x069 /* Wakeup Timer 0 */
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#define AX5043_WAKEUPTIMER1 0x068 /* Wakeup Timer 1 */
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#define AX5043_WAKEUPXOEARLY 0x06E /* Wakeup Crystal Oscillator Early */
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#define AX5043_XTALAMPL 0xF11 /* Crystal Oscillator Amplitude Control */
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#define AX5043_XTALCAP 0x184 /* Crystal Oscillator Load Capacitance */
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#define AX5043_XTALOSC 0xF10 /* Crystal Oscillator Control */
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#define AX5043_XTALSTATUS 0x01D /* Crystal Oscillator Status */
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#define AX5043_0xF00 0xF00
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#define AX5043_0xF0C 0xF0C
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#define AX5043_0xF18 0xF18
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#define AX5043_0xF1C 0xF1C
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#define AX5043_0xF21 0xF21
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#define AX5043_0xF22 0xF22
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#define AX5043_0xF23 0xF23
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#define AX5043_0xF26 0xF26
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#define AX5043_0xF30 0xF30
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#define AX5043_0xF31 0xF31
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#define AX5043_0xF32 0xF32
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#define AX5043_0xF33 0xF33
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#define AX5043_0xF34 0xF34
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#define AX5043_0xF35 0xF35
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#define AX5043_0xF44 0xF44
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#define AX5043_AGCAHYST0 0x122 /* AGC Analog Hysteresis */
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#define AX5043_AGCAHYST1 0x132 /* AGC Analog Hysteresis */
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#define AX5043_AGCAHYST2 0x142 /* AGC Analog Hysteresis */
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#define AX5043_AGCAHYST3 0x152 /* AGC Analog Hysteresis */
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#define AX5043_AGCGAIN0 0x120 /* AGC Speed */
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#define AX5043_AGCGAIN1 0x130 /* AGC Speed */
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#define AX5043_AGCGAIN2 0x140 /* AGC Speed */
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#define AX5043_AGCGAIN3 0x150 /* AGC Speed */
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#define AX5043_AGCMINMAX0 0x123 /* AGC Analog Update Behaviour */
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#define AX5043_AGCMINMAX1 0x133 /* AGC Analog Update Behaviour */
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#define AX5043_AGCMINMAX2 0x143 /* AGC Analog Update Behaviour */
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#define AX5043_AGCMINMAX3 0x153 /* AGC Analog Update Behaviour */
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#define AX5043_AGCTARGET0 0x121 /* AGC Target */
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#define AX5043_AGCTARGET1 0x131 /* AGC Target */
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#define AX5043_AGCTARGET2 0x141 /* AGC Target */
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#define AX5043_AGCTARGET3 0x151 /* AGC Target */
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#define AX5043_AMPLITUDEGAIN0 0x12B /* Amplitude Estimator Bandwidth */
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#define AX5043_AMPLITUDEGAIN1 0x13B /* Amplitude Estimator Bandwidth */
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#define AX5043_AMPLITUDEGAIN2 0x14B /* Amplitude Estimator Bandwidth */
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#define AX5043_AMPLITUDEGAIN3 0x15B /* Amplitude Estimator Bandwidth */
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#define AX5043_BBOFFSRES0 0x12F /* Baseband Offset Compensation Resistors */
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#define AX5043_BBOFFSRES1 0x13F /* Baseband Offset Compensation Resistors */
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#define AX5043_BBOFFSRES2 0x14F /* Baseband Offset Compensation Resistors */
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#define AX5043_BBOFFSRES3 0x15F /* Baseband Offset Compensation Resistors */
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#define AX5043_DRGAIN0 0x125 /* Data Rate Estimator Bandwidth */
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#define AX5043_DRGAIN1 0x135 /* Data Rate Estimator Bandwidth */
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#define AX5043_DRGAIN2 0x145 /* Data Rate Estimator Bandwidth */
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#define AX5043_DRGAIN3 0x155 /* Data Rate Estimator Bandwidth */
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#define AX5043_FOURFSK0 0x12E /* Four FSK Control */
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#define AX5043_FOURFSK1 0x13E /* Four FSK Control */
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#define AX5043_FOURFSK2 0x14E /* Four FSK Control */
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#define AX5043_FOURFSK3 0x15E /* Four FSK Control */
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#define AX5043_FREQDEV00 0x12D /* Receiver Frequency Deviation 0 */
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#define AX5043_FREQDEV01 0x13D /* Receiver Frequency Deviation 0 */
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#define AX5043_FREQDEV02 0x14D /* Receiver Frequency Deviation 0 */
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#define AX5043_FREQDEV03 0x15D /* Receiver Frequency Deviation 0 */
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#define AX5043_FREQDEV10 0x12C /* Receiver Frequency Deviation 1 */
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#define AX5043_FREQDEV11 0x13C /* Receiver Frequency Deviation 1 */
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#define AX5043_FREQDEV12 0x14C /* Receiver Frequency Deviation 1 */
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#define AX5043_FREQDEV13 0x15C /* Receiver Frequency Deviation 1 */
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#define AX5043_FREQUENCYGAINA0 0x127 /* Frequency Estimator Bandwidth A */
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#define AX5043_FREQUENCYGAINA1 0x137 /* Frequency Estimator Bandwidth A */
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#define AX5043_FREQUENCYGAINA2 0x147 /* Frequency Estimator Bandwidth A */
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#define AX5043_FREQUENCYGAINA3 0x157 /* Frequency Estimator Bandwidth A */
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#define AX5043_FREQUENCYGAINB0 0x128 /* Frequency Estimator Bandwidth B */
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#define AX5043_FREQUENCYGAINB1 0x138 /* Frequency Estimator Bandwidth B */
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#define AX5043_FREQUENCYGAINB2 0x148 /* Frequency Estimator Bandwidth B */
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#define AX5043_FREQUENCYGAINB3 0x158 /* Frequency Estimator Bandwidth B */
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#define AX5043_FREQUENCYGAINC0 0x129 /* Frequency Estimator Bandwidth C */
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#define AX5043_FREQUENCYGAINC1 0x139 /* Frequency Estimator Bandwidth C */
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#define AX5043_FREQUENCYGAINC2 0x149 /* Frequency Estimator Bandwidth C */
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#define AX5043_FREQUENCYGAINC3 0x159 /* Frequency Estimator Bandwidth C */
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#define AX5043_FREQUENCYGAIND0 0x12A /* Frequency Estimator Bandwidth D */
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#define AX5043_FREQUENCYGAIND1 0x13A /* Frequency Estimator Bandwidth D */
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#define AX5043_FREQUENCYGAIND2 0x14A /* Frequency Estimator Bandwidth D */
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#define AX5043_FREQUENCYGAIND3 0x15A /* Frequency Estimator Bandwidth D */
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#define AX5043_FREQUENCYLEAK 0x116 /* Baseband Frequency Recovery Loop Leakiness */
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#define AX5043_PHASEGAIN0 0x126 /* Phase Estimator Bandwidth */
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#define AX5043_PHASEGAIN1 0x136 /* Phase Estimator Bandwidth */
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#define AX5043_PHASEGAIN2 0x146 /* Phase Estimator Bandwidth */
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#define AX5043_PHASEGAIN3 0x156 /* Phase Estimator Bandwidth */
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#define AX5043_PKTADDR0 0x207 /* Packet Address 0 */
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#define AX5043_PKTADDR1 0x206 /* Packet Address 1 */
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#define AX5043_PKTADDR2 0x205 /* Packet Address 2 */
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#define AX5043_PKTADDR3 0x204 /* Packet Address 3 */
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#define AX5043_PKTADDRCFG 0x200 /* Packet Address Config */
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#define AX5043_PKTADDRMASK0 0x20B /* Packet Address Mask 0 */
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#define AX5043_PKTADDRMASK1 0x20A /* Packet Address Mask 1 */
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#define AX5043_PKTADDRMASK2 0x209 /* Packet Address Mask 2 */
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#define AX5043_PKTADDRMASK3 0x208 /* Packet Address Mask 3 */
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#define AX5043_PKTLENCFG 0x201 /* Packet Length Configuration */
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#define AX5043_PKTLENOFFSET 0x202 /* Packet Length Offset */
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#define AX5043_PKTMAXLEN 0x203 /* Packet Maximum Length */
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#define AX5043_RXPARAMCURSET 0x118 /* Receiver Parameter Current Set */
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#define AX5043_RXPARAMSETS 0x117 /* Receiver Parameter Set Indirection */
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#define AX5043_TIMEGAIN0 0x124 /* Time Estimator Bandwidth */
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#define AX5043_TIMEGAIN1 0x134 /* Time Estimator Bandwidth */
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#define AX5043_TIMEGAIN2 0x144 /* Time Estimator Bandwidth */
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#define AX5043_TIMEGAIN3 0x154 /* Time Estimator Bandwidth */
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// power states
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#define AX5043_PWRSTATE_POWERDOWN 0x0
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#define AX5043_PWRSTATE_DEEPSLEEP 0x1
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#define AX5043_PWRSTATE_REGS_ON 0x4
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#define AX5043_PWRSTATE_XTAL_ON 0x5
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#define AX5043_PWRSTATE_FIFO_ON 0x7
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#define AX5043_PWRSTATE_SYNTH_RX 0x8
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#define AX5043_PWRSTATE_FULL_RX 0x9
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#define AX5043_PWRSTATE_WOR_RX 0xb
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#define AX5043_PWRSTATE_SYNTH_TX 0xc
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#define AX5043_PWRSTATE_FULL_TX 0xd
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//fifo commands
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#define AX5043_FIFOCMD_NOP 0x00
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#define AX5043_FIFOCMD_DATA 0x01
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#define AX5043_FIFOCMD_REPEATDATA 0x02
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#define AX5043_FIFOCMD_TIMER 0x10
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#define AX5043_FIFOCMD_RSSI 0x11
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#define AX5043_FIFOCMD_FREQOFFS 0x12
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#define AX5043_FIFOCMD_RFFREQOFFS 0x13
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#define AX5043_FIFOCMD_DATARATE 0x14
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#define AX5043_FIFOCMD_ANTRSSI 0x15
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#define AX5043_FIFOCMD_TXCTRL 0x1C
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#define AX5043_FIFOCMD_TXPWR 0x1D
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#define SILICONREV1 0x51
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\
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#define RADIO_OK 0
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#define RADIO_ERR_REVISION 1
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#define RADIO_ERR_COMM 2
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#define RADIO_ERR_IRQ 3
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#define RADIO_ERR_WAKEUPTIMEOUT 4
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#define PKTDATA_BUFLEN 260
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typedef enum {
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trxstate_off,
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trxstate_rx,
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trxstate_rxwor,
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trxstate_wait_xtal,
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trxstate_xtal_ready,
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trxstate_pll_ranging,
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trxstate_pll_ranging_done,
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trxstate_pll_settling,
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trxstate_pll_settled,
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trxstate_tx_xtalwait,
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trxstate_tx_longpreamble,
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trxstate_tx_shortpreamble,
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trxstate_tx_packet,
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trxstate_tx_waitdone,
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trxstate_txcw_xtalwait,
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trxstate_txstream_xtalwait,
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trxstate_txstream
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} axradio_trxstate_t;
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struct axradio_address_mask {
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uint8_t addr[4];
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uint8_t mask[4];
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};
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void axradio_wait_for_xtal(void);
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#endif /* AX5043INIT_H_ */
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