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583 lines
20 KiB
583 lines
20 KiB
/*
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* A sample application transmitting AFSK at 1200 baud
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*
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* Portions Copyright (C) 2018 Libre Space Foundation
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* Portions Copyright (C) 2018 Jonathan Brandenburg
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef AX5043_H_
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#define AX5043_H_
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#include <stdint.h>
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#define FREQUENCY_OFFSET -80000
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#define APRS_VHF 440390000
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/******************************************************************************
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************************* RF Configuration ***********************************
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*****************************************************************************/
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#define RX_FREQ_HZ (APRS_VHF + FREQUENCY_OFFSET)
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#define TX_FREQ_HZ (APRS_VHF + FREQUENCY_OFFSET)
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/* Reference Oscillator frequency */
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#define XTAL_FREQ_HZ 16000000
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/**
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* The maximum allowed frame size
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*/
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#define MAX_FRAME_LEN 1024
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#define RX_BAUDRATE 1200
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#define TX_BAUDRATE 1200
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#define MIN_RF_FREQ_INT_VCO_RFDIV0 800000000
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#define MAX_RF_FREQ_INT_VCO_RFDIV0 1050000000
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#define MIN_RF_FREQ_INT_VCO_RFDIV1 (MIN_RF_FREQ_INT_VCO_RFDIV0 / 2)
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#define MAX_RF_FREQ_INT_VCO_RFDIV1 (MAX_RF_FREQ_INT_VCO_RFDIV0 / 2)
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#define MIN_RF_FREQ_EXT_VCO_RFDIV0 54000000
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#define MAX_RF_FREQ_EXT_VCO_RFDIV0 525000000
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#define MIN_RF_FREQ_EXT_VCO_RFDIV1 (MIN_RF_FREQ_EXT_VCO_RFDIV0 / 2)
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#define MAX_RF_FREQ_EXT_VCO_RFDIV1 (MAX_RF_FREQ_EXT_VCO_RFDIV0 / 2)
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/**
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* Ramp up/Ramp down period of the power amplifier in microseconds
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*/
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#define PWRAMP_RAMP_PERIOD_US 200
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/******************************************************************************
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******************** AX5043 control SPI registers ***************************
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*****************************************************************************/
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/* Status and test registers */
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#define AX5043_REG_REV 0x0
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#define AX5043_REG_SCRATCH 0x1
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/* Power and voltage regulator */
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#define AX5043_REG_PWRMODE 0x2
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#define AX5043_REG_POWSTAT 0x3
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#define AX5043_REG_POWSTICKYSTAT 0x4
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#define AX5043_REG_POWIRQMASK 0x5
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/* Interrupt control */
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#define AX5043_REG_IRQMASK1 0x6
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#define AX5043_REG_IRQMASK0 0x7
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#define AX5043_REG_RADIOEVENTMASK1 0x8
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#define AX5043_REG_RADIOEVENTMASK0 0x9
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#define AX5043_REG_IRQREQUEST1 0xC
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#define AX5043_REG_IRQREQUEST0 0xD
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#define AX5043_REG_RADIOEVENTREQ1 0xE
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#define AX5043_REG_RADIOEVENTREQ0 0xF
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/* Modulation and framing */
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#define AX5043_REG_MODULATION 0x010
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#define AX5043_REG_ENCODING 0x011
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#define AX5043_REG_FRAMING 0x012
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#define AX5043_REG_CRCINIT3 0x014
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#define AX5043_REG_CRCINIT2 0x015
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#define AX5043_REG_CRCINIT1 0x016
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#define AX5043_REG_CRCINIT0 0x017
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/* FEC */
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#define AX5043_REG_FEC 0x018
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#define AX5043_REG_FECSYNC 0x019
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#define AX5043_REG_FECSTATUS 0x01A
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/* Status */
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#define AX5043_REG_RADIOSTATE 0x01C
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#define AX5043_REG_XTALSTATUS 0x01D
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/* Pin configuration */
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#define AX5043_REG_PINSTATE 0x20
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#define AX5043_REG_PINFUNCSYSCLK 0x21
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#define AX5043_REG_PINFUNCDCLK 0x22
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#define AX5043_REG_PINFUNCDATA 0x23
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#define AX5043_REG_PINFUNCIRQ 0x24
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#define AX5043_REG_PINFUNCANTSEL 0x25
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#define AX5043_REG_PINFUNCPWRAMP 0x26
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#define AX5043_REG_PWRAMP 0x27
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/* FIFO control */
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#define AX5043_REG_FIFOSTAT 0x28
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#define AX5043_REG_FIFODATA 0x29
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#define AX5043_REG_FIFOCOUNT1 0x2A
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#define AX5043_REG_FIFOCOUNT0 0x2B
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#define AX5043_REG_FIFOFREE1 0x2C
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#define AX5043_REG_FIFOFREE0 0x2D
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#define AX5043_REG_FIFOTHRESH1 0x2E
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#define AX5043_REG_FIFOTHRESH0 0x2F
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/* Frequency Synthesizer */
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#define AX5043_REG_PLLLOOP 0x30
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#define AX5043_REG_PLLCPI 0x31
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#define AX5043_REG_PLLVCODIV 0x32
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#define AX5043_REG_PLLRANGINGA 0x33
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#define AX5043_REG_FREQA3 0x34
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#define AX5043_REG_FREQA2 0x35
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#define AX5043_REG_FREQA1 0x36
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#define AX5043_REG_FREQA0 0x37
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#define AX5043_REG_PLLLOOPBOOST 0x38
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#define AX5043_REG_PLLCPIBOOST 0x39
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#define AX5043_REG_PLLRANGINGB 0x3B
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#define AX5043_REG_FREQB3 0x3C
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#define AX5043_REG_FREQB2 0x3D
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#define AX5043_REG_FREQB1 0x3E
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#define AX5043_REG_FREQB0 0x3F
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/* RSSI */
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#define AX5043_REG_RSSI 0x40
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#define AX5043_REG_BGNDRSSI 0x41
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#define AX5043_REG_DIVERSITY 0x42
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#define AX5043_REG_AGCCOUNTER 0x43
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/* Receiver Tracking */
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#define AX5043_REG_TRKDATARATE2 0x45
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#define AX5043_REG_TRKDATARATE1 0x46
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#define AX5043_REG_TRKDATARATE0 0x47
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#define AX5043_REG_TRKAMPL1 0x48
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#define AX5043_REG_TRKAMPL0 0x49
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#define AX5043_REG_TRKPHASE1 0x4A
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#define AX5043_REG_TRKPHASE0 0x4B
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#define AX5043_REG_TRKRFFREQ2 0x4D
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#define AX5043_REG_TRKRFFREQ1 0x4E
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#define AX5043_REG_TRKRFFREQ0 0x4F
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#define AX5043_REG_TRKFREQ1 0x50
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#define AX5043_REG_TRKFREQ0 0x51
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#define AX5043_REG_TRKFSKDEMOD1 0x52
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#define AX5043_REG_TRKFSKDEMOD0 0x53
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/* Timers */
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#define AX5043_REG_TIMER2 0x59
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#define AX5043_REG_TIMER1 0x5A
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#define AX5043_REG_TIMER0 0x5B
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/* Wakeup timer */
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#define AX5043_REG_WAKEUPTIMER1 0x68
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#define AX5043_REG_WAKEUPTIMER0 0x69
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#define AX5043_REG_WAKEUP1 0x6A
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#define AX5043_REG_WAKEUP0 0x6B
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#define AX5043_REG_WAKEUPFREQ1 0x6C
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#define AX5043_REG_WAKEUPFREQ0 0x6D
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#define AX5043_REG_WAKEUPXOEARLY 0x6E
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/* PHY related registers*/
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#define AX5043_REG_IFFREQ1 0x100
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#define AX5043_REG_IFFREQ0 0x101
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#define AX5043_REG_DECIMATION 0x102
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#define AX5043_REG_RXDATARATE2 0x103
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#define AX5043_REG_RXDATARATE1 0x104
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#define AX5043_REG_RXDATARATE0 0x105
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#define AX5043_REG_MAXDROFFSET2 0x106
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#define AX5043_REG_MAXDROFFSET1 0x107
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#define AX5043_REG_MAXDROFFSET0 0x108
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#define AX5043_REG_MAXRFOFFSET2 0x109
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#define AX5043_REG_MAXRFOFFSET1 0x10A
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#define AX5043_REG_MAXRFOFFSET0 0x10B
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#define AX5043_REG_FSKDMAX1 0x10C
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#define AX5043_REG_FSKDMAX0 0x10D
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#define AX5043_REG_FSKDMIN1 0x10E
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#define AX5043_REG_FSKDMIN0 0x10F
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#define AX5043_REG_AFSKSPACE1 0x110
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#define AX5043_REG_AFSKSPACE0 0x111
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#define AX5043_REG_AFSKMARK1 0x112
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#define AX5043_REG_AFSKMARK0 0x113
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#define AX5043_REG_AFSKCTRL 0x114
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#define AX5043_REG_AMPLFILTER 0x115
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#define AX5043_REG_FREQUENCYLEAK 0x116
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#define AX5043_REG_RXPARAMSETS 0x117
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#define AX5043_REG_RXPARAMCURSET 0x118
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/* Receiver Parameter Set 0 */
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#define AX5043_REG_AGCGAIN0 0x120
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#define AX5043_REG_AGCTARGET0 0x121
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#define AX5043_REG_AGCAHYST0 0x122
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#define AX5043_REG_AGCMINMAX0 0x123
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#define AX5043_REG_TIMEGAIN0 0x124
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#define AX5043_REG_DRGAIN0 0x125
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#define AX5043_REG_PHASEGAIN0 0x126
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#define AX5043_REG_FREQGAINA0 0x127
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#define AX5043_REG_FREQGAINB0 0x128
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#define AX5043_REG_FREQGAINC0 0x129
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#define AX5043_REG_FREQGAIND0 0x12A
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#define AX5043_REG_AMPLGAIN0 0x12B
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#define AX5043_REG_FREQDEV10 0x12C
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#define AX5043_REG_FREQDEV00 0x12D
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#define AX5043_REG_FOURFSK0 0x12E
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#define AX5043_REG_BBOFFSRES0 0x12F
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/* Receiver Parameter Set 1 */
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#define AX5043_REG_AGCGAIN1 0x130
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#define AX5043_REG_AGCTARGET1 0x131
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#define AX5043_REG_AGCAHYST1 0x132
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#define AX5043_REG_AGCMINMAX1 0x133
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#define AX5043_REG_TIMEGAIN1 0x134
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#define AX5043_REG_DRGAIN1 0x135
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#define AX5043_REG_PHASEGAIN1 0x136
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#define AX5043_REG_FREQGAINA1 0x137
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#define AX5043_REG_FREQGAINB1 0x138
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#define AX5043_REG_FREQGAINC1 0x139
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#define AX5043_REG_FREQGAIND1 0x13A
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#define AX5043_REG_AMPLGAIN1 0x13B
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#define AX5043_REG_FREQDEV11 0x13C
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#define AX5043_REG_FREQDEV01 0x13D
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#define AX5043_REG_FOURFSK1 0x13E
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#define AX5043_REG_BBOFFSRES1 0x13F
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/* Receiver Parameter Set 2 */
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#define AX5043_REG_AGCGAIN2 0x140
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#define AX5043_REG_AGCTARGET2 0x141
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#define AX5043_REG_AGCAHYST2 0x142
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#define AX5043_REG_AGCMINMAX2 0x143
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#define AX5043_REG_TIMEGAIN2 0x144
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#define AX5043_REG_DRGAIN2 0x145
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#define AX5043_REG_PHASEGAIN2 0x146
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#define AX5043_REG_FREQGAINA2 0x147
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#define AX5043_REG_FREQGAINB2 0x148
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#define AX5043_REG_FREQGAINC2 0x149
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#define AX5043_REG_FREQGAIND2 0x14A
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#define AX5043_REG_AMPLGAIN2 0x14B
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#define AX5043_REG_FREQDEV12 0x14C
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#define AX5043_REG_FREQDEV02 0x14D
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#define AX5043_REG_FOURFSK2 0x14E
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#define AX5043_REG_BBOFFSRES2 0x14F
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/* Receiver Parameter Set 3 */
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#define AX5043_REG_AGCGAIN3 0x150
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#define AX5043_REG_AGCTARGET3 0x151
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#define AX5043_REG_AGCAHYST3 0x152
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#define AX5043_REG_AGCMINMAX3 0x153
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#define AX5043_REG_TIMEGAIN3 0x154
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#define AX5043_REG_DRGAIN3 0x155
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#define AX5043_REG_PHASEGAIN3 0x156
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#define AX5043_REG_FREQGAINA3 0x157
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#define AX5043_REG_FREQGAINB3 0x158
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#define AX5043_REG_FREQGAINC3 0x159
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#define AX5043_REG_FREQGAIND3 0x15A
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#define AX5043_REG_AMPLGAIN3 0x15B
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#define AX5043_REG_FREQDEV13 0x15C
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#define AX5043_REG_FREQDEV03 0x15D
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#define AX5043_REG_FOURFSK3 0x15E
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#define AX5043_REG_BBOFFSRES3 0x15F
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/* Transmitter Parameters */
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#define AX5043_REG_MODCFGF 0x160
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#define AX5043_REG_FSKDEV2 0x161
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#define AX5043_REG_FSKDEV1 0x162
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#define AX5043_REG_FSKDEV0 0x163
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#define AX5043_REG_MODCFGA 0x164
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#define AX5043_REG_TXRATE2 0x165
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#define AX5043_REG_TXRATE1 0x166
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#define AX5043_REG_TXRATE0 0x167
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#define AX5043_REG_TXPWRCOEFFA1 0x168
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#define AX5043_REG_TXPWRCOEFFA0 0x169
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#define AX5043_REG_TXPWRCOEFFB1 0x16A
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#define AX5043_REG_TXPWRCOEFFB0 0x16B
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#define AX5043_REG_TXPWRCOEFFC1 0x16C
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#define AX5043_REG_TXPWRCOEFFC0 0x16D
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#define AX5043_REG_TXPWRCOEFFD1 0x16E
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#define AX5043_REG_TXPWRCOEFFD0 0x16F
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#define AX5043_REG_TXPWRCOEFFE1 0x170
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#define AX5043_REG_TXPWRCOEFFE0 0x171
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/* PLL parameters */
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#define AX5043_REG_PLLVCOI 0x180
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#define AX5043_REG_PLLVCOIR 0x181
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#define AX5043_REG_PLLLOCKDET 0x182
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#define AX5043_REG_PLLRNGCLK 0x183
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/* Crystal Oscillator */
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#define AX5043_REG_XTALCAP 0x184
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/* Baseband */
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#define AX5043_REG_BBTUNE 0x188
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#define AX5043_REG_BBOFFSCAP 0x189
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/* MAC parameters */
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/* Packet Format */
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#define AX5043_REG_PKTADDRCFG 0x200
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#define AX5043_REG_PKTLENCFG 0x201
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#define AX5043_REG_PKTLENOFFSET 0x202
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#define AX5043_REG_PKTMAXLEN 0x203
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#define AX5043_REG_PKTADDR3 0x204
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#define AX5043_REG_PKTADDR2 0x205
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#define AX5043_REG_PKTADDR1 0x206
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#define AX5043_REG_PKTADDR0 0x207
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#define AX5043_REG_PKTADDRMASK3 0x208
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#define AX5043_REG_PKTADDRMASK2 0x209
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#define AX5043_REG_PKTADDRMASK1 0x20A
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#define AX5043_REG_PKTADDRMASK0 0x20B
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/* Pattern Match */
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#define AX5043_REG_MATCH0PAT3 0x210
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#define AX5043_REG_MATCH0PAT2 0x211
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#define AX5043_REG_MATCH0PAT1 0x212
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#define AX5043_REG_MATCH0PAT0 0x213
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#define AX5043_REG_MATCH0LEN 0x214
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#define AX5043_REG_MATCH0MIN 0x215
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#define AX5043_REG_MATCH0MAX 0x216
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#define AX5043_REG_MATCH1PAT1 0x218
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#define AX5043_REG_MATCH1PAT0 0x219
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#define AX5043_REG_MATCH1LEN 0x21C
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#define AX5043_REG_MATCH1MIN 0x21D
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#define AX5043_REG_MATCH1MAX 0x21E
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/* Packet Controller */
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#define AX5043_REG_TMGTXBOOST 0x220
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#define AX5043_REG_TMGTXSETTLE 0x221
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#define AX5043_REG_TMGRXBOOST 0x223
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#define AX5043_REG_TMGRXSETTLE 0x224
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#define AX5043_REG_TMGRXOFFSACQ 0x225
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#define AX5043_REG_TMGRXCOARSEAGC 0x226
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#define AX5043_REG_TMGRXAGC 0x227
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#define AX5043_REG_TMGRXRSSI 0x228
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#define AX5043_REG_TMGRXPREAMBLE1 0x229
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#define AX5043_REG_TMGRXPREAMBLE2 0x22A
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#define AX5043_REG_TMGRXPREAMBLE3 0x22B
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#define AX5043_REG_RSSIREFERENCE 0x22C
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#define AX5043_REG_RSSIABSTHR 0x22D
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#define AX5043_REG_BGNDRSSIGAIN 0x22E
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#define AX5043_REG_BGNDRSSITHR 0x22F
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#define AX5043_REG_PKTCHUNKSIZE 0x230
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#define AX5043_REG_PKTMISCFLAGS 0x231
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#define AX5043_REG_PKTSTOREFLAGS 0x232
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#define AX5043_REG_PKTACCEPTFLAGS 0x233
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/* Special Functions */
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/* General Purpose ADC */
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#define AX5043_REG_GPADCCTRL 0x300
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#define AX5043_REG_GPADCPERIOD 0x301
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#define AX5043_REG_GPADC13VALUE1 0x308
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#define AX5043_REG_GPADC13VALUE0 0x309
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/* Low Power Oscillator Calibration */
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#define AX5043_REG_LPOSCCONFIG 0x310
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#define AX5043_REG_LPOSCSTATUS 0x311
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#define AX5043_REG_LPOSCKFILT1 0x312
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#define AX5043_REG_LPOSCKFILT0 0x313
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#define AX5043_REG_LPOSCREF1 0x314
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#define AX5043_REG_LPOSCREF0 0x315
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#define AX5043_REG_LPOSCFREQ1 0x316
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#define AX5043_REG_LPOSCFREQ0 0x317
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#define AX5043_REG_LPOSCPER1 0x318
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#define AX5043_REG_LPOSCPER0 0x319
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/* Performance Tuning Registers */
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#define AX5043_REG_XTALDIV 0xF35
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/******************************************************************************
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************************* Register values ************************************
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*****************************************************************************/
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#define AX5043_REV 0x51
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#define AX5043_SCRATCH_TEST 0xAA
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/* Power modes */
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#define AX5043_POWERDOWN 0x0
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#define AX5043_DEEPSLEEP BIT(0)
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#define AX5043_STANDBY (BIT(2) | BIT(0))
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#define AX5043_FIFO_ENABLED (BIT(2) | BIT(1) |BIT(0))
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#define AX5043_RECEIVE_MODE (BIT(3))
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#define AX5043_RECEIVER_RUNNING (BIT(3) | BIT(0))
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#define AX5043_RECEIVER_WOR (BIT(3) | BIT(1) | BIT(0))
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#define AX5043_TRANSMIT_MODE (BIT(3) | BIT(2))
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#define AX5043_TRANSMIT_RUNNING (BIT(3) | BIT(2) | BIT(0))
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#define AX5043_FULLTX AX5043_TRANSMIT_RUNNING
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#define AX5043_PLLVCOI_MANUAL BIT(7)
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/**
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* Modem Domain Voltage Regulator Ready
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*/
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#define AX5043_SVMODEM BIT(3)
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/**
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* Init value for the VCO prior starting an autoranging
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*/
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#define AX5043_VCOR_INIT 8
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#define AX5043_RFDIV0 0x0
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#define AX5043_RFDIV1 BIT(2)
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#define AX5043_FREQSHAPE_EXT_FILTER 0x0
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#define AX5043_FREQSHAPE_INVALID 0x1
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#define AX5043_FREQSHAPE_GAUSSIAN_BT_03 0x2
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#define AX5043_FREQSHAPE_GAUSSIAN_BT_05 0x3
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/**
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* FSK modulation mode
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*/
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#define AX5043_MODULATION_FSK BIT(3)
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/**
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* AFSK modulation mode
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*/
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#define AX5043_MODULATION_AFSK (BIT(3)|BIT(1))
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#define AX5043_ENC_INV BIT(0)
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#define AX5043_ENC_DIFF BIT(1)
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#define AX5043_ENC_SCRAM BIT(2)
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/**
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* HDLC Framing mode
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*/
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#define AX5043_HDLC_FRAMING BIT(2)
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/**
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* HDLC compliant CRC16
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*/
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#define AX5043_CRC16_CCITT BIT(4)
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/**
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* Set the FIFO to variable length data mode
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*/
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#define AX5043_FIFO_VARIABLE_DATA_CMD 0xe1
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#define AX5043_FIFO_REPEATDATA_CMD (BIT(6) | BIT(5) | BIT(1))
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/**
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* FIFO commit command
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*/
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#define AX5043_FIFO_COMMIT_CMD BIT(2)
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#define AX5043_FIFO_PKTSTART BIT(0)
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#define AX5043_FIFO_PKTEND BIT(1)
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#define AX5043_FIFO_NOCRC BIT(3)
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#define AX5043_FIFO_RAW BIT(4)
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/**
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* Maximum chuck that can be committed on the FIFO
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*/
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#define AX5043_PKTCHUNKSIZE_240 0xd
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#define AX5043_FIFO_MAX_SIZE 240
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/**
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* When this threshold of free bytes in the TX FIFO is reached,
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* we'll put more data in the FIFO
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*/
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#define AX5043_FIFO_FREE_THR 128
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/**
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* TX antenna transmission mode
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*/
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#define AX5043_TX_SINGLE_ENDED BIT(1)
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#define AX5043_TX_DIFFERENTIAL BIT(0)
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/**
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* External PA Control
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*/
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#define AX5043_EXT_PA_ENABLE 1
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#define AX5043_EXT_PA_DISABLE 0
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/**
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* Frequency mode A or B actually selects at which registers
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* the frequency configuration should be written.
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*
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* This is quite handy for different RX/TX frequencies, to avoid
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* writing every time the two different frequency configurations.
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*/
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typedef enum {
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FREQA_MODE = 0, //!< FREQA_MODE
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FREQB_MODE = 1 //!< FREQB_MODE
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} freq_mode_t;
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typedef enum {
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VCO_INTERNAL = 0, VCO_EXTERNAL = 1
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} vco_mode_t;
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typedef enum {
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POWERDOWN,
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DEEPSLEEP,
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STANDBY,
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FIFO_ENABLED,
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RECEIVE_MODE,
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RECEIVER_RUNNING,
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RECEIVER_WOR,
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TRANSMIT_MODE,
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FULLTX
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} power_mode_t;
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|
|
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typedef struct {
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|
uint32_t tx_freq;
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uint32_t rx_freq;
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uint32_t f_xtal;
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uint8_t f_xtaldiv;
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|
uint32_t tx_baudrate;
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|
uint32_t rx_baudrate;
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|
uint8_t rf_init;
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freq_mode_t freqsel;
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|
vco_mode_t vco;
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} ax5043_conf_t;
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|
|
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int ax5043_reset_a(ax5043_conf_t *conf);
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|
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int ax5043_init(ax5043_conf_t *conf, uint32_t f_xtal, vco_mode_t vco);
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|
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int ax5043_conf_tx_path(ax5043_conf_t *conf);
|
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|
|
int ax5043_set_tx_freq(ax5043_conf_t *conf, uint32_t freq);
|
|
|
|
int ax5043_set_power_mode(ax5043_conf_t *conf, power_mode_t mode);
|
|
|
|
int ax5043_set_tx_baud(ax5043_conf_t *conf, uint32_t baud);
|
|
|
|
int ax5043_freqsel(ax5043_conf_t *conf, freq_mode_t f);
|
|
|
|
int ax5043_set_tx_synth(ax5043_conf_t *conf);
|
|
|
|
int ax5043_set_pll_params(ax5043_conf_t *conf);
|
|
|
|
int ax5043_autoranging(ax5043_conf_t *conf);
|
|
|
|
int ax5043_aprs_framing_setup(ax5043_conf_t *conf);
|
|
|
|
int ax5043_tx_frame(ax5043_conf_t *conf, const uint8_t *in, uint32_t len,
|
|
uint8_t preamble_len, uint8_t postamble_len, uint32_t timeout_ms);
|
|
|
|
int ax5043_spi_wait_xtal(ax5043_conf_t *conf, uint32_t timeout_ms);
|
|
|
|
int ax5043_spi_read_8(ax5043_conf_t *conf, uint8_t *out, uint16_t reg);
|
|
|
|
int ax5043_spi_read_16(ax5043_conf_t *conf, uint16_t *out, uint16_t reg);
|
|
|
|
int ax5043_spi_read_24(ax5043_conf_t *conf, uint32_t *out, uint16_t reg);
|
|
|
|
int ax5043_spi_read_32(ax5043_conf_t *conf, uint32_t *out, uint16_t reg);
|
|
|
|
int ax5043_spi_write(ax5043_conf_t *conf, uint16_t reg, const uint8_t *in,
|
|
uint32_t len);
|
|
|
|
int ax5043_spi_write_8(ax5043_conf_t *conf, uint16_t reg, uint8_t in);
|
|
|
|
int ax5043_spi_write_16(ax5043_conf_t *conf, uint16_t reg, uint16_t in);
|
|
|
|
int ax5043_spi_write_24(ax5043_conf_t *conf, uint16_t reg, uint32_t in);
|
|
|
|
int ax5043_spi_write_32(ax5043_conf_t *conf, uint16_t reg, uint32_t in);
|
|
|
|
int ax5043_enable_pwramp(ax5043_conf_t *conf, uint8_t enable);
|
|
|
|
int ax5043_set_antsel(ax5043_conf_t *conf, uint8_t val);
|
|
|
|
int ax5043_wait_for_transmit();
|
|
|
|
#endif /* AX5043_H_ */
|