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363 lines
10 KiB
363 lines
10 KiB
/**
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* Digital Voice Modem - DSP Firmware (Hotspot)
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* GPLv2 Open Source. Use is subject to license terms.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* @package DVM / DSP Firmware (Hotspot)
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*
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*/
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//
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// Based on code from the MMDVM_HS project. (https://github.com/juribeparada/MMDVM_HS)
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// Licensed under the GPLv2 License (https://opensource.org/licenses/GPL-2.0)
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//
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/*
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* Copyright (C) 2020 by Jonathan Naylor G4KLX
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* Copyright (C) 2016 by Jim McLaughlin KI6ZUM
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* Copyright (C) 2016,2017,2018 by Andy Uribe CA6JAU
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* Copyright (C) 2017 by Danilo DB4PLE
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* Copyright (C) 2021 Bryan Biedenkapp N2PLL
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*
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* Some of the code is based on work of Guus Van Dooren PE1PLM:
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* https://github.com/ki6zum/gmsk-dstar/blob/master/firmware/dvmega/dvmega.ino
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#if !defined(__ADF7021_H__)
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#define __ADF7021_H__
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#include "Defines.h"
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// ---------------------------------------------------------------------------
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// Constants
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// ---------------------------------------------------------------------------
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#define LOW 0
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#define HIGH 1
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#define DEFAULT_FREQUENCY 433075000
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/** Band Tables */
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/** 136 - 174 mhz */
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#define VHF_MIN 136000000
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#define VHF_MAX 174000000
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/** 216 - 225 mhz */
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#define VHF_220_MIN 216000000
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#define VHF_220_MAX 225000000
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/** 380 - 431mhz */
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#define UHF_380_MIN 380000000
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#define UHF_380_MAX 431000000
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/** 431 - 450mhz */
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#define UHF_1_MIN 431000000
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#define UHF_1_MAX 470000000
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/** 450 - 470mhz */
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#define UHF_2_MIN 450000000
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#define UHF_2_MAX 470000000
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/** 470 - 520mhz (T-band) */
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#define UHF_T_MIN 470000000
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#define UHF_T_MAX 520000000
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/** 842 - 900mhz */
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#define UHF_800_MIN 842000000
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#define UHF_800_MAX 900000000
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/** 900 - 950mhz */
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#define UHF_900_MIN 900000000
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#define UHF_900_MAX 950000000
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#if defined(ENABLE_ADF7021)
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#define ADF_BIT_READ(value, bit) (((value) >> (bit)) & 0x01)
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#define ADF7021_EVEN_BIT false
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#define ADF7021_DISC_BW_MAX 660
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#define ADF7021_POST_BW_MAX 1023
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#if defined(ADF7021_ENABLE_4FSK_AFC)
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#if defined(ADF7021_AFC_POS)
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#define AFC_OFFSET_DMR -125
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#define AFC_OFFSET_P25 -125
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#define AFC_OFFSET_NXDN -125
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#else
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#define AFC_OFFSET_DMR 125
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#define AFC_OFFSET_P25 125
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#define AFC_OFFSET_NXDN 125
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#endif // ADF7021_AFC_POS
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#else
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#define AFC_OFFSET_DMR 0
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#define AFC_OFFSET_P25 0
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#define AFC_OFFSET_NXDN 0
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#endif // ADF7021_ENABLE_4FSK_AFC
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/*
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- Most of the registers values are obteined from ADI eval software:
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http://www.analog.com/en/products/rf-microwave/integrated-transceivers-transmitters-receivers/low-power-rf-transceivers/adf7021.html
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- or ADF7021 datasheet formulas:
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www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
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*/
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/** Test modes */
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// Enable SWD pin to access the demodulator output signal:
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// (See application note AN-852 and ADF7021 datasheet, page 60)
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// #define TEST_DAC
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// Transmit the carrier frequency:
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// #define TEST_TX
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/** Support for 14.7456 MHz TCXO (modified RF7021SE boards) */
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#if defined(ADF7021_14_7456)
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// R = 2, DEMOD_CLK = 7.3728 MHz
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// R = 3, DEMOD_CLK = 4.9152 MHz
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// R = 4, DEMOD_CLK = 3.6864 MHz
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#define ADF7021_PFD 3686400.0
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/*
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** VCO/Oscillator (Register 1)
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*/
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#define ADF7021_REG1_VHF 0x02175041 /** 136 - 174mhz */
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#define ADF7021_REG1_VHF_220 0x021B5041 /** 219 - 225mhz */
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#if defined(FORCE_UHF_INTERAL_L)
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#define ADF7021_REG1_UHF_380 0x001B5041 /** 380 - 431mhz */
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#else
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#define ADF7021_REG1_UHF_380 0x021B5041 /** 380 - 431mhz */ // this could be problematic due to
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// the external VCO control
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#endif // FORCE_UHF_INTERAL_L
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#define ADF7021_REG1_UHF_1 0x00575041 /** 431 - 450mhz */
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#define ADF7021_REG1_UHF_2 0x01D75041 /** 450 - 470mhz */
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#if defined(FORCE_UHF_INTERAL_L)
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#define ADF7021_REG1_UHF_T 0x00235041 /** 470 - 520mhz */
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#else
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#define ADF7021_REG1_UHF_T 0x02235041 /** 470 - 520mhz */ // this could be problematic due to
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// the external VCO control
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#endif // FORCE_UHF_INTERAL_L
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#define ADF7021_REG1_800 0x00535041 /** 842 - 900mhz */
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#define ADF7021_REG1_900 0x01D35041 /** 900 - 950mhz */
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/*
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** Transmit Modulation (Register 2)
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*/
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#define ADF7021_DEV_DEFAULT 43U
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#define ADF7021_DEV_DMR 23U
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#if defined(ENABLE_P25_WIDE)
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#define ADF7021_DEV_P25 32U
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#else
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#define ADF7021_DEV_P25 22U
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#endif // ENABLE_P25_WIDE
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#define ADF7021_DEV_NXDN 13U
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/*
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** Demodulator Setup (Register 4)
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*/
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// Discriminator bandwith, demodulator
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// Bug in ADI evaluation software, use datasheet formula (4FSK)
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#define ADF7021_DISC_BW_DEFAULT 522U // K=85
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#define ADF7021_DISC_BW_DMR 393U // K=32
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#define ADF7021_DISC_BW_P25 393U // K=32
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#define ADF7021_DISC_BW_NXDN 295U // K=32
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// Post demodulator bandwith
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#define ADF7021_POST_BW_DEFAULT 10U
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#define ADF7021_POST_BW_DMR 80U
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#define ADF7021_POST_BW_P25 6U
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#define ADF7021_POST_BW_NXDN 7U
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/*
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** IF Coarse Cal Setup (Register 5)
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*/
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#define ADF7021_REG5 0x000024F5
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/*
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** IF Fine Cal Setup (Register 6)
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*/
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#define ADF7021_REG6 0x05070E16
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/** Support for 12.2880 MHz TCXO */
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#elif defined(ADF7021_12_2880)
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// R = 2, DEMOD_CLK = 6.1440 MHz
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// R = 3, DEMOD_CLK = 4.0960 MHz
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// R = 4, DEMOD_CLK = 3.0720 MHz
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#define ADF7021_PFD 6144000.0
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/*
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** VCO/Oscillator (Register 1)
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*/
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#define ADF7021_REG1_VHF 0x02175021 /** 136 - 174mhz */
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#define ADF7021_REG1_VHF_220 0x021B5021 /** 219 - 225mhz */
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#if defined(FORCE_UHF_INTERAL_L)
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#define ADF7021_REG1_UHF_380 0x001B5021 /** 380 - 431mhz */
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#else
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#define ADF7021_REG1_UHF_380 0x021B5021 /** 380 - 431mhz */ // this could be problematic due to
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// the external VCO control
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#endif // FORCE_UHF_INTERAL_L
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#define ADF7021_REG1_UHF_1 0x00575021 /** 431 - 450mhz */
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#define ADF7021_REG1_UHF_2 0x01D75021 /** 450 - 470mhz */
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#if defined(FORCE_UHF_INTERAL_L)
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#define ADF7021_REG1_UHF_T 0x00235021 /** 470 - 520mhz */
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#else
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#define ADF7021_REG1_UHF_T 0x02235021 /** 470 - 520mhz */ // this could be problematic due to
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// the external VCO control
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#endif // FORCE_UHF_INTERAL_L
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#define ADF7021_REG1_800 0x00535021 /** 842 - 900mhz */
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#define ADF7021_REG1_900 0x01D35021 /** 900 - 950mhz */
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/*
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** Transmit Modulation (Register 2)
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*/
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#define ADF7021_DEV_DEFAULT 26U
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#define ADF7021_DEV_DMR 14U
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#if defined(ENABLE_P25_WIDE)
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#define ADF7021_DEV_P25 19U
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#else
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#define ADF7021_DEV_P25 13U
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#endif // ENABLE_P25_WIDE
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#define ADF7021_DEV_NXDN 8U
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/*
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** Demodulator Setup (Register 4)
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*/
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// Discriminator bandwith, demodulator
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// Bug in ADI evaluation software, use datasheet formula (4FSK)
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#define ADF7021_DISC_BW_DEFAULT 522U // K=85
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#define ADF7021_DISC_BW_DMR 491U // K=32
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#define ADF7021_DISC_BW_P25 491U // K=32
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#define ADF7021_DISC_BW_NXDN 246U // K=32
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// Post demodulator bandwith
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#define ADF7021_POST_BW_DEFAULT 10U
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#define ADF7021_POST_BW_DMR 80U
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#define ADF7021_POST_BW_P25 6U
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#define ADF7021_POST_BW_NXDN 8U
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/*
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** IF Coarse Cal Setup (Register 5)
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*/
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#define ADF7021_REG5 0x00001ED5
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/*
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** IF Fine Cal Setup (Register 6)
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*/
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#define ADF7021_REG6 0x0505EBB6
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#endif // ADF7021_12_2880
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/*
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** N Register (Register 0)
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*/
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#define ADF7021_REG0_ADDR 0b0000
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/*
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** Transmit Modulation (Register 2)
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*/
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#define ADF7021_REG2_ADDR 0b0010
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#define ADF7021_REG2_MOD_GMSK 0b001
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#define ADF7021_REG2_MOD_4FSK 0b011
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#define ADF7021_REG2_MOD_4FSKRC 0b111
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#define ADF7021_REG2_PA_DEF 0b110001
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#define ADF7021_REG2_INV_NORM 0b00
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#define ADF7021_REG2_INV_CLK 0b01
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#define ADF7021_REG2_INV_DATA 0b10
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#define ADF7021_REG2_INV_CLKDAT 0b11
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#define ADF7021_REG2_RC_5 0b0
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#define ADF7021_REG2_RC_7 0b1
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/*
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** Tx/Rx Clock (Register 3)
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*/
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#define ADF7021_REG3_ADDR 0b0011
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// Baseband Offset Clock Divider
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#define ADF7021_REG3_BBOS_DIV_4 0b00
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#define ADF7021_REG3_BBOS_DIV_8 0b01
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#define ADF7021_REG3_BBOS_DIV_16 0b10
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#define ADF7021_REG3_BBOS_DIV_32 0b11
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/*
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** Demodulator Setup (Register 4)
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*/
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#define ADF7021_REG4_ADDR 0b0100
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#define ADF7021_REG4_MODE_GMSK 0b001
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#define ADF7021_REG4_MODE_4FSK 0b011
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#define ADF7021_REG4_CROSS_PROD 0b0
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#define ADF7021_REG4_DOT_PROD 0b1
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#define ADF7021_REG4_INV_NORM 0b00
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#define ADF7021_REG4_INV_CLK 0b01
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#define ADF7021_REG4_INV_DATA 0b10
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#define ADF7021_REG4_INV_CLKDAT 0b11
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#define ADF7021_REG4_IF_125K 0b00
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#define ADF7021_REG4_IF_1875K 0b01
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#define ADF7021_REG4_IF_25K 0b10
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/*
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** AFC (Register 10)
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*/
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#define ADF7021_REG10_ADDR 0b1010
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#define ADF7021_REG10_AFC_DISABLE 0b0
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#define ADF7021_REG10_AFC_ENABLE 0b1
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/*
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** 3FSK/4FSK Demod (Register 13)
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*/
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#define ADF70210_REG13_ADDR 0b1101
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// Slicer threshold for 4FSK demodulator
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#define ADF7021_SLICER_TH_DEFAULT 0U
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#if defined(ADF7021_N_VER)
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#define ADF7021_SLICER_TH_DMR 51U
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#define ADF7021_SLICER_TH_P25 43U
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#define ADF7021_SLICER_TH_NXDN 26U
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#else
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#define ADF7021_SLICER_TH_DMR 57U
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#define ADF7021_SLICER_TH_P25 47U
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#define ADF7021_SLICER_TH_NXDN 26U
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#endif // ADF7021_N_VER
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#endif // ENABLE_ADF7021
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#endif // __ADF7021_H__
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